1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the device, which can be applied to, for example, an LSI (large scale integrated circuit) involving multi-layered interconnection.
2. Description of the Related Art
Recently, the essential parts of computers or communication devices use, in most cases, an LSI circuit in which a great number of transistors and resistances are coupled with each other to form an electric circuit structure and integrated on a chip. With this structure, the performance of the entire device depends greatly on the performance of each single unit of the LSI circuits used in the device. Therefore, the performance of the LSI circuit can be improved by, for example, increasing the degree of integration, that is, reducing the size of the elements that constitute the LSI circuit. In order to actually realize the reduction of size of these elements, it is necessary to reduce the size of the wiring section for connecting one element with another and to increase the number of wiring layers.
However, at the same time, as a result of reducing the size of the wiring section and increasing the number of layers, that have been advanced in order to meet the demand of reducing the size of elements, the following drawback has become prominent. That is, the resistance of the conductive layer itself and the parasitic capacity between wiring sections (interwiring capacity, inter-layer capacity, etc.) are increased, thereby causing more signal delay.
Under the circumstances, in order to reduce the parasitic capacity between the conductive layers, a method of decreasing the specific inductive capacity of an interlayer insulating film has been proposed. However, the reduction of the specific inductive capacity by this method is limited due to the physical properties and the like of the material.
In the meantime, there has been proposal of a method of, for example, reducing the opposing area between conductive layers (or reducing the thickness of the wiring film) while lowering the specific inductive capacity of the interlayer insulating film. However, with this method, the resistance value of the conductive layer is increased due to a decrease in the thickness of the film, although it is possible to decrease the parasitic capacity.
Under the circumstances, recently, the use of an aluminum (Al)-based conductive layer, which is conventionally used, has been switched to the use of a copper (Cu)-based conductive layer, Cu having a resistance value about 40% lower than that of Al, in order to reduce the wiring resistance. (See, for example, Jpn. Pat. Appln. KOKAI Publication No. H11-186273.)
However, the thickness of each conductive layer is significantly reduced due to the increase in the number of conductive layers and the reduction in the size of layers, and therefore the current density, etc. of the conductive layer is increased. Thus, even with a Cu-based conductive layer such as mentioned above, the lowering of the reliability is inevitable. Further, in the case of the Cu-based conductive layer, Cu in the boundary between wiring layers, especially in a lower layer side, is diffused, which results in the lowering of the reliability. Thus, switching from the Al-based conductive layer to the Cu-based conductive layer makes it possible to reduce the wiring resistance; however at the same time, the best method of lowering the interlayer capacity acts in reverse, and causes the lowering of the reliability of the conductive layer.